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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max1295/max1297 low-power, 12-bit analog-to- digital converters (adcs) feature a successive-approxi- mation adc, automatic power-down, fast wake-up (2s), on-chip clock, +2.5v internal reference, and high-speed 12-bit parallel interface. they operate with a single +2.7v to +3.6v analog supply. power consumption is only 5.4mw at the maximum sampling rate of 265ksps. two software-selectable power-down modes enable the max1295/max1297 to be shut down between conversions; accessing the par- allel interface returns them to normal operation. powering down between conversions can reduce sup- ply current below 10a at lower sampling rates. both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differen- tial operation. in single-ended mode, the max1295 has six input channels and the max1297 has two (three input channels and one input channel, respectively, when in pseudo-differential mode). excellent dynamic performance and low power combined with ease of use and small package size make these con- verters ideal for battery-powered and data-acquisition applications or for other circuits with demanding power- consumption and space requirements. the max1295 is offered in a 28-pin qsop package, while the max1297 comes in a 24-pin qsop. for pin-compatible +5v, 12-bit versions, refer to the max1294/max1296 data sheet. applications industrial control systems data logging energy management patient monitoring data-acquisition systems touchscreens features ? 12-bit resolution, 0.5lsb linearity ? +3v single-supply operation ? internal +2.5v reference ? software-configurable analog input multiplexer 6-channel single-ended/ 3-channel pseudo-differential (max1295) 2-channel single-ended/ 1-channel pseudo-differential (max1297) ? software-configurable unipolar/bipolar analog inputs ? low current 1.8ma (265ksps) 1.0ma (100ksps) 400a (10ksps) 2a (shutdown) ? internal 3mhz full-power bandwidth track/hold ? parallel 12-bit interface ? small footprint 28-pin qsop (max1295) 24-pin qsop (max1297) max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface ________________________________________________________________ maxim integrated products 1 19-1530; rev 0; 9/99 evaluation kit available 28 qsop 1 0c to +70c MAX1295BCEI inl (lsb) 0.5 28 qsop pin-package temp. range 0c to +70c max1295 acei part ordering information pin configurations typical operating circuits appear at end of data sheet. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d10 d11 v dd ref refadj gnd cs com ch0 ch1 ch2 ch3 ch4 ch5 clk wr rd int d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 qsop top view max1295 pin configurations continued at end of data sheet. 28 qsop 0.5 -40c to +85c max1295aeei 28 qsop 1 -40c to +85c max1295beei 24 qsop 0.5 -40c to +85c max1297aeeg 24 qsop 1 -40c to +85c max1297beeg 24 qsop 1 0c to +70c max1297bceg 0.5 24 qsop 0c to +70c max1297 aceg
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7f capacitor at ref pin, f clk = 4.8mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ch0Cch5, com to gnd ............................-0.3v to (v dd + 0.3v) ref, refadj to gnd.................................-0.3v to (v dd + 0.3v) digital inputs to gnd ...............................................-0.3v to +6v digital outputs (d0Cd11, int ) to gnd.......-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70c) 24-pin qsop (derate 9.5mw/c above +70c)..........762mw 28-pin qsop (derate 8.00mw/c above +70c)........667mw operating temperature ranges max1295_c_ _ /max1297_c_ _ ........................0c to +70c max1295_e_ _ /max1297_e_ _ ......................-40c to +85c storage temperature range .............................-65c to +150c lead temperature (soldering, 10sec) .............................+300c external acquisition or external clock mode internal acquisition/internal clock mode max129_a external acquisition/internal clock mode external clock mode -3db rolloff sinad > 68db f in = 125khz (note 4) f in1 = 49khz, f in2 = 52khz max129_b no missing codes over temperature conditions ns 50 aperture delay ns 625 t acq track/hold acquisition time 3.2 3.6 4.1 2.5 3.0 3.5 s 3.3 t conv conversion time (note 5) mhz 3 full-power bandwidth khz 250 full-linear bandwidth db -78 channel-to-channel crosstalk db 76 imd intermodulation distortion db 80 sfdr spurious-free dynamic range db total harmonic distortion (including 5th-order harmonic) -78 thd 0.5 inl relative accuracy (note 2) bits 12 res resolution db 67 70 sinad signal-to-noise plus distortion lsb 0.2 channel-to-channel offset matching ppm/c 2.0 gain temperature coefficient lsb 1 lsb 1 dnl differential nonlinearity lsb 4 offset error lsb 4 gain error (note 3) units min typ max symbol parameter internal acquisition/internal clock mode external acquisition or external clock mode <200 ps <50 aperture jitter mhz 0.1 4.8 f clk external clock frequency % 30 70 duty cycle dc accuracy (note 1) dynamic specifications (f in(sine-wave) = 50khz, v in = 2.5vp-p, 265ksps, external f clk = 4.8mhz, bipolar input mode) conversion rate
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7f capacitor at ref pin, f clk = 4.8mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) conditions units min typ max symbol parameter 0 to 0.5ma output load to power down the internal reference for small adjustments on/off-leakage-current, v in = 0 or v dd unipolar, v com = 0 bipolar, v com = v ref /2 v 1.0 v dd + 50mv v ref ref input voltage range f 4.7 10 capacitive bypass at ref f 0.01 1 capacitive bypass at refadj mv/ma 0.2 0.5 load regulation (note 7) v v dd - 1 refadj high threshold mv 100 refadj input range ma 15 ref short-circuit current v 2.49 2.5 2.51 ref output voltage pf 12 c in input capacitance a 0.01 1 multiplexer leakage current v 0 v ref analog input voltage range single-ended and differential (note 6) -v ref /2 +v ref /2 v in cs = v dd i source = 1ma i sink = 1.6ma v in = 0 or v dd v ref = 2.5v, f sample = 265ksps a 0.1 1 i leakage three-state leakage current v v dd - 0.5 v oh output voltage high v 0.4 v ol output voltage low pf 15 c in input capacitance a 0.1 1 i in input leakage current mv 200 v hys input hysteresis v 0.8 v il input voltage low v 2.0 v ih input voltage high a 200 300 i ref ref input current cs = v dd v 2.7 3.6 v dd analog supply voltage pf 15 c out three-state output capacitance internal reference 2.3 2.6 ppm/c 20 tc ref ref temperature coefficient shutdown mode 2 external reference 1.9 2.3 0.9 1.2 positive supply current shutdown mode 210 a power-supply rejection psr v dd = 2.7v to 3.6v, full-scale input 0.4 0.7 mv i dd 0.5 0.8 ma operating mode, f sample = 265ksps internal reference external reference standby mode conversion rate (continued) analog inputs internal reference external reference at ref digital inputs and outputs power requirements
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 4 _______________________________________________________________________________________ t tr 20 70 ns c load = 20pf, figure 1 rd rise to output disable wr to clk fall setup time t cws 40 ns ns clk pulse width high ns clk period t ch 40 rd fall to output data valid t do 20 70 ns rd fall to int high delay t int1 100 ns cs fall to output data valid t do2 110 ns c load = 20pf, figure 1 c load = 20pf, figure 1 c load = 20pf, figure 1 t cp 208 clk pulse width low t cl 40 ns data valid to wr rise time t ds 40 ns wr rise to data valid hold time t dh 0 ns clk fall to wr hold time t cwh 40 ns cs to clk or wr setup time t csws 60 ns clk or wr to cs hold time t cswh 0 ns cs pulse width t cs 100 ns wr pulse width (note 8) t wr 60 ns t tc 20 100 ns c load = 20pf, figure 1 parameter symbol min typ max units conditions cs rise to output disable note 1: tested at v dd = +3v, com = gnd, unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. note 3: offset nulled. note 4: on channel is grounded; sine wave applied to off channels. note 5: conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. note 6: input voltage range referenced to negative input. the absolute range for the analog inputs is from gnd to v dd . note 7: external load should not change during conversion for specified accuracy. note 8: when bit 5 is set low for internal acquisition, wr must not return low until after the first falling clock edge of the conversion. timing characteristics (v dd = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7f capacitor at ref pin, f clk = 4.8mhz (50% duty cycle), t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) 6k gnd gnd 3k dout dout v dd a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol c load 20pf c load 20pf figure 1. load circuits for enable/disable times
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 5 -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 integral nonlinearity vs. digital output code max1295/7-01 digital output code inl (lsb) -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 differential nonlinearity vs. digital output code max1295/7-02 digital output code dnl (lsb) 1.80 1.90 1.85 2.00 1.95 2.05 2.10 2.7 3.0 3.3 3.6 supply current vs. supply voltage max1295/7 toc03 v dd (v) i dd (ma) r l = code = 101010100000 1.6 1.8 1.7 2.0 1.9 2.1 2.2 -40 10 -15 35 60 85 supply current vs. temperature max1295/7 toc04 temperature ( c) i dd (ma) r l = code = 101010100000 880 890 910 900 920 930 standby current vs. supply voltage max1295/7 toc05 v dd (v) standby i dd ( m a) 2.7 3.3 3.0 3.6 880 890 910 900 920 930 standby current vs. temperature max1295/7 toc06 temperature ( c) standby i dd ( m a) -40 10 -15 35 85 60 0.50 1.00 0.75 1.25 1.50 2.7 3.0 3.3 3.6 power-down current vs. supply voltage max1295/7 toc07 v dd (v) power-down i dd ( m a) 0.8 0.9 1.0 1.1 1.2 power-down current vs. temperature max1295/7 toc08 temperature ( c) power-down i dd ( m a) -40 35 -15 10 60 85 typical operating characteristics (v dd = +3v, v ref = +2.500v, f clk = 4.8mhz, c l = 20pf, t a = +25c, unless otherwise noted.) 0.1 1k 100k 10 1 100 10k 1m supply current vs. sample frequency max1295/7-02a f sample (hz) i dd ( m a) 0 10 100 1000 10,000 with external reference with internal reference
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = +3v, v ref = +2.500v, f clk = 4.8mhz, c l = 20pf, t a = +25c, unless otherwise noted.) max1295/7-10 v ref (ma) 85 2.48 2.49 2.51 2.50 2.52 2.53 internal reference voltage vs. temperature temperature (?) -40 60 35 10 -15 -2.5 -2.0 -1.0 -1.5 -0.5 0 offset error vs. supply voltage max1295/7 toc11 v dd (v) offset error (lsb) 2.7 3.3 3.0 3.6 -2.5 -1.5 -2.0 -0.5 -1.0 0 0.5 -40 10 -15 35 60 85 offset error vs. temperature max1295/7 toc12 temperature (?) offset error (lsb) -3.0 -1.0 -2.0 0 1.0 2.7 3.3 3.0 3.6 gain error vs. supply voltage max1295/7 toc13 v dd (v) gain error (lsb) -2.0 -1.5 -0.5 -1.0 0 0.5 gain error vs. temperature max1295/7 toc14 temperature (?) gain error (lsb) -40 10 -15 35 60 85 max1295/7-09 v ref (v) 3.6 2.48 2.49 2.51 2.50 2.52 2.53 internal reference voltage vs. supply voltage v dd (v) 2.7 3.3 3.0 -140 -120 -100 -80 -60 -40 -20 0 20 0 200 400 600 800 1000 fft plot max1295/7-15 frequency (khz) amplitude (db) v dd = 3v f in = 50khz f sample = 250ksps
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 7 pin description d0 10 10 int 11 11 rd 12 12 wr 13 13 clk 14 14 d4 6 6 d3 7 7 d2 8 8 d1 9 9 d5 5 5 d6 4 4 1 d7 3 3 d8 2 2 d9 1 three-state digital i/o line (d0) int goes low when the conversion is complete and output data is ready. active-low read select. if cs is low, a falling edge on rd will enable the read oper- ation on the data bus. active-low write select. when cs is low in the internal acquisition mode, a rising edge on wr latches in configuration data and starts an acquisition plus a conver- sion cycle. when cs is low in external acquisition mode, the first rising edge on wr ends acquisition and starts a conversion. clock input. in external clock mode, drive clk with a ttl/cmos-compatible clock. in internal clock mode, connect this pin to either v dd or gnd. three-state digital i/o line (d4) three-state digital i/o line (d3) three-state digital i/o line (d2) three-state digital i/o line (d1) three-state digital i/o line (d5) three-state digital i/o line (d6) three-state digital i/o line (d7) three-state digital output (d8) three-state digital output (d9) gnd 19 23 refadj 20 24 ch2 19 ch1 16 20 ch0 17 21 com 18 22 ch3 18 ch4 17 ch5 16 cs 15 15 analog and digital ground bandgap reference output/bandgap reference buffer input. bypass to gnd with a 0.01f capacitor. when using an external reference, connect refadj to v dd to disable the internal bandgap reference. analog input channel 2 analog input channel 1 analog input channel 0 ground reference for analog inputs. sets zero-code voltage in single-ended mode and must be stable to 0.5lsb during conversion. analog input channel 3 analog input channel 4 analog input channel 5 active-low chip select. when cs is high, digital outputs ( int , d11Cd0) are high impedance. pin max1297 max1295 name function
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 8 _______________________________________________________________________________________ pin description (continued) pin max1297 ref 21 25 max1295 name bandgap reference buffer output/external reference input. add a 4.7f capacitor to gnd when using the internal reference. function 26 22 v dd analog +2.7v to +3.6v power supply. bypass with a 0.1f capacitor to gnd. 27 23 d11 three-state digital output (d11) 28 24 d10 three-state digital output (d10) _______________detailed description converter operation the max1295/max1297 adcs use a successive- approximation (sar) conversion technique and an input track/hold (t/h) stage to convert an analog input signal to a 12-bit digital output. this output format provides an easy interface to standard microprocessors (ps). figure 2 shows the simplified internal architecture of the max1295/max1297. single-ended and pseudo-differential operation the sampling architecture of the adcs analog com- parator is illustrated in the equivalent input circuit in figure 3. in single-ended mode, in+ is internally switched to channels ch0Cch5 for the max1295 (figure 3a) and to ch0Cch1 for the max1297 (figure 3b), while in- is switched to com (table 2). in differen- tial mode, in+ and in- are selected from analog input pairs (table 3) and are internally switched to either of t/h three-state, bidirectional i/o interface 12 17k 12 successive- approximation register charge redistribution 12-bit dac clock analog input multiplexer control logic & latches ref refadj 1.22v reference d0?11 12-bit data bus (ch5) (ch4) (ch3) (ch2) ch1 ch0 com clk cs wr rd int ( ) are for max1295 only. v dd gnd max1295 max1297 a v = 2.05 comp figure 2. simplified functional diagram of 6-/2-channel max1295/max1297
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 9 bit pd1, pd0 0 d7, d6 pd1 and pd0 select the various clock and power-down modes. full power-down mode. clock mode is unaffected. d5 acqmod acqmod = 0: internal acquisition mode acqmod = 1: external acquisition mode name functional description 0 1 0 standby power-down mode. clock mode is unaffected. 0 1 1 normal operation mode. external clock mode selected. 1 normal operation mode. internal clock mode selected. d4 sgl /dif sgl /dif = 0: pseudo-differential analog input mode sgl /dif = 1: single-ended analog input mode in single-ended mode, input signals are referred to com. in differential mode, the voltage difference between two channels is measured (tables 2, 4). d3 uni /bip uni/ bip = 0: bipolar mode uni/ bip = 1: unipolar mode in unipolar mode, an analog input signal from 0v to v ref can be converted; in bipolar mode, the signal can range from -v ref /2 to +v ref /2. d2, d1, d0 a2, a1, a0 address bits a2, a1, a0 select which of the 6/2 (max1295/max1297) channels is to be converted (tables 2, 3). table 1. control-byte functional description the analog inputs. this configuration is pseudo-differ- ential in that only the signal at in+ is sampled. the return side (in-) must remain stable within 0.5lsb (0.1lsb for best performance) with respect to gnd during a conversion. to accomplish this, connect a 0.1f capacitor from in- (the selected input) to gnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . at the end of the acquisition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex- er switching c hold from the positive input (in+) to the negative input (in-). this unbalances node zero at the comparators positive input. the capacitive digital- to-analog converter (dac) adjusts during the remain- figure 3a. max1295 simplified input structure figure 3b. max1297 simplified input structure ch0 ch1 ch2 ch3 ch4 ch5 com c switch track t/h switch r in 800 w c hold hold 12-bit capacitive dac v ref zero comparator + 12pf single-ended mode: in+ = ch0?h5, in- = com differential mode: in+ and in- selected from pairs of ch0/ch1 and ch2/ch3, and ch4/ch5 at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux ch0 ch1 com c switch track t/h switch r in 800 w c hold hold 12-bit capacitive dac v ref zero comparator + 12pf single-ended mode: in+ = ch0?h1, in- = com differential mode: in+ and in- selected from pair ch0/ch1 at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 10 ______________________________________________________________________________________ der of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equiv- alent to transferring a 12pf (v in+ - v in- ) charge from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. analog input protection internal protection diodes, which clamp the analog input to v dd and gnd, allow each input channel to swing within (gnd - 300mv) to (v dd + 300mv) without damage. however, for accurate conversions near full scale, both inputs must not exceed (v dd + 50mv) or be less than (gnd - 50mv). if an analog input voltage exceeds the supplies by more than 50mv, limit the forward-bias input current to 4ma. track/hold the max1295/max1297 t/h stage enters its tracking mode on wr s rising edge. in external acquisition mode, the part enters its hold mode on the next rising edge of wr . in internal acquisition mode, the part enters its hold mode on the fourth falling edge of clock after writing the control byte. note that in internal clock mode this is approximately 1s after writing the control byte. in single-ended operation, in- is connected to com and the converter samples the positive + input. in pseudo-differential operation, in- connects to the nega- tive input -, and the difference of | (in+) - (in-) | is sam- pled. at the beginning of the next conversion, the positive input connects back to in+ and chold charges to the input signal. the time required for the t/h stage to acquire an input signal depends on how quickly its input capacitance is charged. if the input signals source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal, and is also the minimum time required for the signal to be acquired. calculate this with the follow- ing equation: t acq = 9 (r s + r in ) c in where r s is the source impedance of the input signal, r in (800 ) is the input resistance, and c in (12pf) is the input capacitance of the adc. source impedances below 3k have no significant impact on the max1295/ max1297s ac performance. higher source impedances can be used if a 0.01f capacitor is connected to the individual analog inputs. a1 ch0 0 + 0 - 0 a0 0 1 ch2* ch4* + - 0 1 0 + ch3* - 0 ch1 com 1 ch5* 1 + - 0 0 0 a2 + - 1 0 1 - + 1 table 2. channel selection for single-ended operation (sgl/ dif = 1) table 3. channel selection for pseudo-differential operation (sgl/ dif = 0) a1 ch0 0 + 0 - 0 a0 0 - 1 ch2* ch4* + 0 1 0 + - ch3* 0 ch1 1 ch5* 1 - + 0 0 0 a2 + - 1 0 1 - + 1 * channels ch2Cch5 apply to max1295 only. * channels ch2Cch5 apply to max1295 only.
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 11 together with the input impedance, this capacitor forms an rc filter, limiting the adcs signal bandwidth. input bandwidth the max1295/max1297 t/h stage offers a 250khz full- linear and a 3mhz full-power bandwidth. this makes it possible to digitize high-speed transients and measure periodic signals with bandwidths exceeding the adcs sampling rate by using undersampling techniques. to avoid high-frequency signals being aliased into the fre- quency band of interest, anti-alias filtering is recom- mended. starting a conversion initiate a conversion by writing a control byte that selects the m ultiplexer channel and configures the max1295/ max1297 for either unipolar or bipolar operation. a write pulse ( wr + cs ) can either start an acquisition interval or initiate a combined acquisition plus conver- sion. the sampling interval occurs at the end of the acquisition interval. the acquisition mode (acqmod) bit in the input control byte (table 1) offers two options for acquiring the signal: an internal and an external acquisition. the conversion period lasts for 13 clock cycles in either the internal or external clock or acquisi- tion mode. writing a new control byte during a conver- sion cycle will abort the conversion and start a new acquisition interval. internal acquisition select internal acquisition by writing the control byte with the acqmod bit cleared (acqmod = 0). this causes the write pulse to initiate an acquisition interval whose duration is internally timed. conversion starts when this acquisition interval (three external clock cycles or approximately 1s in internal clock mode) ends (figure 4). note that when the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode. figure 4. conversion timing using internal acquisition mode t cs t csws t wr t acq t conv t dh t ds t int1 t d0 t tr high-z high-z cs wr d11?0 int rd dout acqmod ="0" valid data control byte t cswh
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 12 ______________________________________________________________________________________ external acquisition use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisi- tion and conversion times. the user controls acquisition and start-of-conversion with two separate write pulses. the first pulse, written with acqmod = 1, starts an acquisition interval of indeterminate length. the second write pulse, written with acqmod = 0 (all other bits in control byte unchanged), terminates acquisition and starts conversion on wr rising edge (figure 5). the address bits for the input multiplexer must have the same values on the first and second write pulse. power-down mode bits (pd0, pd1) can assume new values on the second write pulse (see power-down modes section). changing other bits in the control byte will corrupt the conversion. reading a conversion a standard interrupt signal int is provided to allow the max1295/max1297 to flag the p when the conversion has ended and a valid result is available. int goes low when the conversion is complete and the output data is ready (figures 4, 5). it returns high on the first read cycle or if a new control byte is written. selecting clock mode the max1295/max1297 operate with either an internal or an external clock. control bits d6 and d7 select either internal or external clock mode. the part retains the last requested clock mode if a power-down mode is selected in the current input word. for both internal and external clock mode, internal or external acquisition can be used. at power-up, the max1295/max1297 enter the default external clock mode. internal clock mode select internal clock mode to release the p from the burden of running the sar conversion clock. bits d6 and d7 of the control byte must be set to 1; the internal clock frequency is then selected, resulting in a conver- sion time of 3.6s. when using the internal clock mode, tie the clk pin either high or low to prevent the pin from floating. t cs t csws t wr t acq t conv t dh t ds t int1 t d0 t tr t cswh acqmod = "1" cs wr d11?0 int rd dout acqmod = "0" valid data control byte control byte high-z high-z figure 5. conversion timing using external acquisition mode
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 13 external clock mode to select the external clock mode, bits d6 and d7 of the control byte must be set to zero. figure 6 shows the clock and wr timing relationship for internal (figure 6a) and external (figure 6b) acquisition modes with an external clock. for proper operation, a 100khz to 4.8mhz clock frequency with 30% to 70% duty cycle is recommended. operating the max1295/max1297 with clock frequencies lower than 100khz is not recommend- ed because the resulting voltage droop across the hold capacitor in the t/h stage will degrade performance. digital interface the input and output data are multiplexed on a three- state parallel interface (i/o) that can easily be inter- faced with standard ps. the signals cs , wr , and rd control the write and read operations. cs represents figure 6a. external clock and wr timing (internal acquisition mode) figure 6b. external clock and wr timing (external acquisition mode) wr clk clk wr wr goes high when clk is high. wr goes high when clk is low. t cws t ch t cl t cp t cwh acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "0" acqmod = "0" wr clk clk wr wr goes high when clk is high wr goes high when clk is low t dh t dh t cwh t cws acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "1" acqmod = "1" acqmod = "0" acqmod = "0"
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 14 ______________________________________________________________________________________ the chip-select signal, which enables a p to address the max1295/max1297 as an i/o port. when high, cs disables the clk, wr , and rd inputs and forces the interface into a high-impedance (high-z) state. input format the control bit sequence is latched into the device on pins d7Cd0 during a write command. table 4 shows the control-byte format. output data format the 12-bit-wide output format for both the max1295/ max1297 is binary in unipolar mode and twos comple- ment in bipolar mode. cs , rd , wr , int , and the 12 bits of output data can interface directly to a 16-bit data bus. when reading the output data, cs and rd must be low. __________applications information power-on reset when power is first applied, internal power-on reset cir- cuitry activates the max1295/max1297 in external clock mode and sets int high. after the power supplies stabi- lize, the internal reset time is 10s; no conversions should be attempted during this phase. when using the internal reference, 500s is required for v ref to stabilize. internal and external reference the max1295/max1297 can be used with an internal or external reference voltage. an external reference can be connected directly to ref or refadj. an internal buffer is designed to provide +2.5v at ref for both the max1295 and max1297. the internally trimmed +1.22v reference is buffered with a +2.05v/v gain. internal reference the full-scale range with the internal reference is +2.5v with unipolar inputs and 1.25v with bipolar inputs. the internal reference buffer allows for small adjustments (100mv) in the reference voltage (figure 7). note: the reference buffer must be compensated with an external capacitor (4.7f min) connected between ref and gnd to reduce reference noise and switching spikes from the adc. to further minimize noise on the reference, connect a 0.01f capacitor between refadj and gnd. external reference with both the max1295 and max1297, an external refer- ence can be placed at either the input (refadj) or the output (ref) of the internal reference buffer amplifier. using the refadj input makes buffering the external reference unnecessary. the refadj input impedance is typically 17k . when applying an external reference to ref, disable the internal reference buffer by connecting refadj to v dd . the dc input resistance at ref is 25k . therefore, an external reference at ref must deliver up to 200a dc load current during a conversion and have an output impedance less than 10 . if the refer- ence has higher output impedance or is noisy, bypass it close to the ref pin with a 4.7f capacitor. power-down modes to save power, place the converter in a low-current shutdown state between conversions. select standby mode or shutdown mode through bits d6 and d7 of the control byte (tables 1, 4). in both software power-down modes the parallel interface remains active, but the adc does not convert. standby mode while in standby mode, the supply current is typically 850a. the part will power up on the next rising edge of wr and be ready to perform conversions. this quick turn-on time allows the user to realize significantly reduced power consumption for conversion rates below 265ksps. d6 d4 d5 pd0 sgl/ dif acqmod a2 a0 a1 d2 d0 (lsb) uni /bip pd1 d1 d3 d7 (msb) table 4. control-byte format v dd = +3v 330k 50k gnd gnd 50k 0.01 f 4.7 f refadj ref max1295 max1297 figure 7. reference adjustment with external potentiometer
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 15 shutdown mode shutdown mode turns off all chip functions that draw qui- escent current, reducing the typical supply current to 2a immediately after the current conversion is complet- ed. a rising edge on wr causes the max1295/max1297 to exit shutdown mode and return to normal operation. to achieve full 12-bit accuracy with a 4.7f reference bypass capacitor, 50s is required after power-up. waiting this 50s in standby mode instead of in full- power mode can reduce power consumption by a factor of 3 or more. when using an external reference, only 50s is required after power-up. enter standby mode by performing a dummy conversion with the control byte specifying standby mode. note: bypass capacitors larger than 4.7f between ref and gnd will result in longer power-up delays. transfer function table 5 shows the full-scale voltage ranges for unipolar and bipolar modes. figure 8 depicts the nominal unipo- lar input/output (i/o) transfer function, and figure 9 shows the bipolar i/o transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1lsb = (v ref /4096). maximum sampling rate/ achieving 300ksps when running at the maximum clock frequency of 4.8mhz, the specified throughput of 265ksps is achieved by completing a conversion every 18 clock cycles: 1 write cycle, 3 acquisition cycles, 13 conversion cycles, and 1 read cycle. this assumes that the results of the last conversion are read before the next control byte is written. it is possible to achieve higher throughputs, up to 300ksps, by first writing a control byte to begin the table 5. full-scale and zero-scale for unipolar and bipolar operation 111 . . . 111 111 . . . 110 100 . . . 010 100 . . . 001 100 . . . 000 011 . . . 111 011 . . . 110 011 . . . 101 000 . . . 001 000 . . . 000 1 0 input voltage (lsb) output code zs = com fs = ref + com 1lsb = ref 4096 full-scale transition (com) fs - 3/2lsb fs 2 2048 unipolar mode bipolar mode v ref + com v ref /2 + com positive full scale full scale com com zero scale zero scale -v ref /2 + com negative full scale figure 8. unipolar transfer function 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = com +fs - 1lsb *com v ref /2 + com fs = ref 2 -fs = + com -ref 2 1lsb = ref 4096 figure 9. bipolar transfer function
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 16 ______________________________________________________________________________________ acquisition cycle of the next conversion, and then read- ing the results of the previous conversion from the bus. this technique (figure 10) allows a conversion to be completed every 16 clock cycles. note that the switch- ing of the data bus during acquisition or conversion can cause additional supply noise, which may make it diffi- cult to achieve true 12-bit performance. layout, grounding, and bypassing for best performance, use printed circuit (pc) boards. wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. do not run analog and digital lines parallel to each other, and dont lay out digital signal paths underneath the adc package. use separate analog and digital pc board ground sections with only one star point (figure 11) connecting the two ground systems (analog and digital). for lowest noise opera- tion, ensure the ground return to the star grounds power supply is low impedance and as short as possi- ble. route digital signals far away from sensitive analog and reference inputs. high-frequency noise in the power supply, v dd , could impair operation of the adcs fast comparator. bypass v dd to the star ground with a network of two parallel capacitors, 0.1f and 4.7f, located as close as to the max1295/max1297s power-supply pin as possible. minimize capacitor lead length for best supply-noise rejection and add an attenuation resistor (5 ) if the power supply is extremely noisy. figure 11. power-supply and grounding connections figure 10. timing diagram for fastest conversion +3v +3v gnd supplies dgnd +3v com gnd 4.7 m f 0.1 m f v dd digital circuitry max1295 max1297 *r = 5 w *optional clk acquisition control word conversion d11?0 acquisition sampling instant 123 4 5 6 78 910111213141516 wr rd d7?0 state control word d11e d0
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 17 _________________________definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the max1295/max1297 is measured using the end- point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution, (n bits): snr = (6.02 n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys rms amplitude to rms equivalent of all other adc output signals: sinad (db) = 20 log (signal rms / noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v1 is the fundamental amplitude, and v2 through v5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component. thd v v v v v =+++ ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log / chip information transistor count: 5781 substrate connected to gnd
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface 18 ______________________________________________________________________________________ typical operating circuits v dd ref refadj int ch5 ch4 ch3 ch2 ch1 ch0 com gnd 4.7 m f 0.1 m f +3v +2.5v output status m p control inputs clk cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 m p data bus d8 d9 d10 d11 analog inputs max1295 v dd ref refadj int ch1 ch0 com gnd 4.7 m f 0.1 m f +3v +2.5v output status m p control inputs clk cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 m p data bus d8 d9 d10 d11 analog inputs max1297
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 19 pin configurations (continued) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 d10 d11 v dd ref refadj gnd com ch0 ch1 cs clk wr rd int d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 qsop top view max1297
max1295/max1297 265ksps, +3v, 6-/2-channel, 12-bit adcs with +2.5v reference and parallel interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. qsop.eps package information

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